The present invention relates to a field memory using a DRAM core accessed in accordance with RAS control signals generated in the integrated circuit.
Conventionally, in a field memory, a DRAM core is not controlled with an external signal but is controlled in accordance with internal signals. Self-refreshing process is also controlled by internal signals, generated inside the integrated circuit. According to such a conventional field memory, a RAS request signal (REQ) is internally generated in response to an external read/write request signal. In response to the RAS request signal (REQ), a RAS control signal (RAS1Z) is generated. In some cases, it is required to generate RAS controls signals in a particular order determined according to the priorities of the RAS request signals.
According to the above described conventional field memory, when a read/write request signal is inputted, for example, seven RAS request signals (REQ) are generated in the order of priority. In response to the RAS request signals, seven cycles of RAS control signal (RAS1Z) is supplied in the order of the REQ""s priority. Each cycle of the RAS control signal RAS1Z has a cycle of 150 ns. The seven cycles of RAS control signal RAS1Z may include cycles for self-refreshing process. In most case, it is required that the seven cycles of the RAS control signal RAS1Z is generated in a certain period of time, such as 1200 ns. With a failure field memory, the seven cycles of the RAS control signal RAS1Z is not generated in the required period of time. The RAS control signal RAS1Z is generated inside the integrated circuit, and therefore, it is difficult to find out failure products.
Accordingly, an object of the present invention is to provide a RAS cycle monitor circuit which can determine whether RAS control signals are generated on a proper cycle.
Another object of the present invention is to provide a field memory in which it can be determined whether RAS control signals are generated on a proper cycle.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a RAS cycle monitor circuit includes a counter circuit, which counts the number of RAS control signals supplied to a DRAM core in a predetermined period of time to decide whether the RAS control signals are generated on a proper cycle.
According to a second aspect of the present invention, a field memory includes a DRAM core; a processor which generates and supplies RAS control signals to the DRAM core; and a RAS cycle monitor circuit which monitors the cycle of the RAS controls signals. The RAS cycle monitor circuit includes a counter circuit which counts the number of RAS control signals supplied to the DRAM core in a predetermined period of time to decide whether the RAS control signals are generated on a proper cycle.
According to the present invention, it can be monitored whether the cycle of RAS control signals is in an acceptable period of time.